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Manohara D
staff Engineer at Mediatek
About
Manohara D is a highly skilled Staff Engineer at Mediatek with a passion for VLSI Physical design. With over 6 years of relevant experience, Manohara has gained a deep understanding of the intricacies involved in designing and implementing complex VLSI circuits. Currently working as a Physical Design Staff Engineer at Mediatek, Manohara is responsible for designing and optimizing the physical layout of integrated circuits. He has a strong background in EDA tools and methodologies, and is adept at using industry-standard tools such as Cadence and Synopsys. Prior to joining Mediatek, Manohara worked as a Physical Design Engineer at Cerium Systems, where he was responsible for designing and implementing physical layouts for U2 chips. He also worked as a Physical Design Engineer at Aricent, where he gained valuable experience in designing and optimizing high-speed and low-power circuits. Manohara holds a Bachelor of Engineering degree in Electrical, Electronics and Communications Engineering from Channabasaveshwara Institute of Technology. During his time at university, he gained a solid foundation in the fundamentals of electronics and communications, which has proved invaluable in his career as a VLSI Physical Design Engineer. Overall, Manohara is a highly motivated and skilled engineer with a keen interest in VLSI Physical design. He is always looking for new challenges and opportunities to learn and grow in his field, and is committed to delivering high-quality results for his clients and employers.
Education Overview
• channabasaveshwara institute of technology
Companies Overview
• mediatek
• cerium systems
• aricent
• rvvlsi vlsi and embedded systems design center
Experience Overview
7.8 Years
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Experience
Skills
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basic electronics
C
Clock Tree Synthesis
CMOS
congestion
Design
design compiler
Design Optimization
Design Rule Checking (DRC)
floorplan
IC Compiler
Layout Design
Layout Versus Schematic (LVS)
Leadership
Linux
Logic Design
Network Theory
perl scripting
placement and optimization
power planning
prime power
Project Management
Questasim
RTL Design
RTL Verification
Semiconductors
Shell Scripting
Static Timing Analysis
Synopsys Primetime
TCL
Verilog
Very-Large-Scale Integration (VLSI)
vlsi
Contact Details
Email (Verified)
dmaXXXXXXXXXXXXXXXXXXXomMobile Number
+91XXXXXXXXXXEducation
channabasaveshwara institute of technology
Bachelor of Engineering (B.E.)
2011 - 2015
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