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Mayank Dhananiwala
Senior Member of Technical Staff
Education
• sutherland hdl
• manipal academy of higher education
• cranes international software pvt ltd.
• jawaharlal nehru technological university
• vignan vidyalayam
• ravi high school nirmal andhra pradesh
Companies
• amd
• cadence design systems
• opensilicon
• seagate
• qualcomm
• whizchip design technologies pvt ltd
• smartplay technologies
• microchip technology
• intel
• paramount technologies
Experience
13.8 Years
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Experience
Synthesis & STA Design/Implementation Engineer
whizchip design technologies pvt ltd | Hyderabad Area, India
2012 - 2013
Skills
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ASIC
asic
Automation
C (Programming Language)
Collaboration
Debugging
Design
Design Flows development/enhancement and automation.
Digital Electronics
Drive Full chip Methodologies Netlisting and Timing Closure
Drive Full Chip RTL-Integration & STA
Drive STA & Synthesis activities
eda
Electronics
Full Chip Netlisting and Timing.
Fullchip Constraints Development
Hardware
Hierarchical ASIC design flows (RTL2NETLIST)
html
Integration
JSON
Knowledge of Hardware description language VHDL, Verilog, System Verilog.
optimization
Perl
Physical Design
Power optimization flows
Presentations
Programming Language experience with C, C+, Shell, Perl, TCl, HTML.
Scripting
Scripting experience with shell, TCL and Perl.
Semiconductor Industry
Semiconductors
Software Engineer
Stakeholder Management
Static Timing analysis.
Synthesis of Complex Designs.
System on a Chip (SoC)
TCL
test
Tester Determinism Mode - STA
Timing Eco
Timing – Signoff
Verilog
VHDL
xml
Contact Details
Email (Verified)
mayXXXXXXXXXXXXXXXXXXXXXXomMobile Number
+91XXXXXXXX28Education
sutherland hdl
Verilog/SystemVerilog for Design
2011 - 2011
manipal academy of higher education
M.S
2009 - 2011
cranes international software pvt ltd.
Advanced PG Diploma
2008 - 2009
jawaharlal nehru technological university
B.Tech
2004 - 2008
vignan vidyalayam
12th
2002 - 2004
ravi high school nirmal andhra pradesh
L.KG - S.S.C
1991 - 2002
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