About

Mayank Pandey is an experienced Design and Verification professional with over 8 years of experience in the EDA industry. He possesses a strong understanding of Functional Verification, Coverage driven verification, Assertion based verification, System Verilog, UVM, C, C++, Python, and is currently exploring/pursuing numerous possibilities of Machine Learning and AI applications in EDA domain. As a Member of Consulting Staff at Cadence Design Systems, Mayank is working towards solving major challenges within the verification workflow by bringing in a new perspective of how to use AI & Machine Learning. He is passionate about exploring the potential of AI and ML in the EDA industry and is constantly looking for ways to improve the workflow using these technologies. Mayank completed his Bachelor of Technology in Electrical, Electronics and Communications Engineering from Motivational Pathway. He has a strong tech stack that includes AI, ML, and Python. With over 10.61 years of relevant experience, Mayank has a proven track record of delivering high-quality work and has gained a reputation as a reliable and skilled professional in the EDA industry. In summary, Mayank Pandey is a highly motivated and skilled Design and Verification professional with a passion for exploring the possibilities of AI and Machine Learning in the EDA industry. He is an asset to any team, and his expertise and experience make him a valuable member of the Cadence Design Systems team.