About

Mohammed Jaseem is a Senior Mixed Signal Design, Modeling & Verification Engineer at Cadence Design Systems with 5 years of experience in the field. He has expertise in SystemVerilog, Verilog-AMS Electrical, VAMS Wreal, UVM-MS, SV-RNM, Tcl, Perl, and Makefile. Currently, he is working on Mixed Signal Verification of Charger Chips and High Bandwidth Memory Interface - HBM3io. Jaseem has experience in Behavioral model development of analog blocks using VAMS/Wreal modeling, including LDO, Charge Pump, SAR ADC, VCO, Signal Generator, Low pass filter, Integrator, Differentiator, Forced Fixed Rate Sampler, ADC, DAC, Inverter, and Amplifier. He has developed UVM and SV TB from scratch and has worked on Functional, gate level, and Mixed Signal verification of chips. Jaseem is skilled in analyzing specifications and creating simulation plans as part of verification planning. He sets up detailed test scenarios using SYSTEM VERILOG/VERILOG-AMS to cover all functionalities and reports bugs to the digital/analog design team. He also performs coverage analysis in Cadence Incisive Metrics Center, such as Toggle, Block, and Expression analysis, and helps in increasing coverage by adding new test cases and covering all signals of the RTL. Jaseem has automated verification environments using Perl and is proficient in working with design sync commands in UNIX environments. He has worked on preparing result documents and presentations. Jaseem holds a Bachelor of Technology degree in Applied Electronics and Instrumentation from the College of Engineering, Trivandrum, with a relevant experience of 4.87 years. Prior to his current position, he has worked with HCL as an Analog/Mixed Signal Design & Verification Engineer and with Siliconch as an Analog/Mixed Signal Design, Modeling & Verification Engineer.