About

Naman Maheshwari is a skilled CPU RTL Designer currently working at NVIDIA as a Senior Logic Design Engineer. He has over 6 years of relevant experience in the field. Naman's expertise lies in designing and implementing logic for measuring activities in CPU core and caches, enabling power savings by DVFS, and minimizing idle power consumption by implementing coarse/fine-grained clock gating. Before joining NVIDIA, Naman worked as a Senior Engineer at Samsung SARC | ACL, where he was part of the Globals RTL team responsible for power and clock management architecture and micro-architecture for CPU. He also assisted the DV team in writing directed functional test sequences for verifying targeted parts of the design. Naman has a Master of Science degree in Electrical and Computer Engineering (Integrated Circuits and Systems) from The University of Texas at Austin, where he worked as a Graduate Teaching Assistant for the course EE 316 (Digital Logic Design) and developed labs based on designing in Verilog and simulation on Basys3 Artix-7 FPGA board. He also holds a Bachelor's degree in Electrical and Electronics Engineering from BITS Pilani. In addition to his professional experience, Naman has a strong technical background in designer, test, neural networks, frontend, and research scientist. He is a highly motivated individual who is passionate about his work and is always eager to learn new skills. Naman's proficiency in CPU RTL design and his ability to work collaboratively make him an asset to any team.