About

Neel Kamal is an Associate Staff Engineer at Samsung, specializing in RTL Design. With over 4 years of relevant experience, he has a proven track record of implementing data-path architecture for artificial intelligence in Verilog. He possesses extensive experience in designing controllers for modules, FSM based coding, and linear and nonlinear modules in Verilog. Neel has also worked on video codec AV1, where he generated test vector YUV for codec verification and has experience in code and functional coverage. He is well-versed in System Verilog, Assertion Based Verification, clock domain crossing, lint check, constraint random test bench, and has knowledge of unified power formats and universal verification methodology. In addition to his design expertise, Neel has experience in building test environments based on OOPS for various patterns like Mat, Mat+, and March for memory testing. He has also worked on assertion-based verification to cover various specifications of memory. Neel is proficient in programming languages such as C, C++, and OOPS and has experience in scripting languages such as Perl and Shell. He is well-versed in tools such as Incisive, Genus, and Conforml. Neel holds a Master of Technology degree in Information and Communication Engineering from the Indian Institute of Engineering Science and Technology (IIEST), Shibpur, and a Bachelor of Engineering degree in Electronics and Telecommunication from Savitribai Phule Pune University. Neel's past experience includes working as a Design Engineer (Client location) at Xilinx and as an Associate Member Technical Staff at DXCorr Design. With his strong technical skills and experience, Neel is a valuable asset to any team.