About

Pankaj Khandelwal is a seasoned Low Power Technologist with over 15 years of experience in the field. He has a deep understanding of different aspects of low power design and verification, ranging from RTL power optimization to sign-off power estimation. Pankaj is skilled in assisting designers and verification engineers in developing UPF aware implementation and verification methodologies, and has a thorough understanding of Logic Equivalence Checking (LEC) and functional-ECO with Conformal-ECO. Apart from his technical expertise, Pankaj is also a compassionate mentor who is passionate about helping others develop their skills and grow as leaders. He has a strong communication skill set that is crucial for application engineering roles. Currently, Pankaj works as a Senior Principal Application Engineer at Cadence Design Systems, where he collaborates with the methodology team at top customer to prepare the tool, flow, and methodology even before the project is on the horizon. Pankaj has worked with several top semiconductor companies during his career, including Synopsys, where he partnered with LP sign-off teams to create an LP verification methodology and trained designers on the IEEE 1801 standard. At Jasper Design Automation, he worked as a Verification IP Developer, where he maintained assertion IPs for Jasper Gold formal verification tool. Pankaj is pursuing an executive MBA from the Indian Institute of Management Kozhikode (IIMK), where he is developing a fair understanding of leadership, marketing, and corporate finance. He tries to apply these concepts in his current role whenever possible and has tasted success in this domain. Pankaj holds a Master of Technology in Electrical Engineering (Instrumentation) from IIT and a BE degree in Instrumentation from the University of Rajasthan.