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Pawan Pareek
asic design verification engineer
About
Pawan Pareek is an experienced ASIC Design Verification Engineer with over 7 years of experience in IP/SOC Verification. He is skilled in System Verilog, UVM, and Python, and has experience in IP/Subsystem/SOC Design Verification. Currently, he works at Google as an ASIC Design Verification Engineer. Prior to his current role, Pawan worked at Qualcomm as a Senior Lead Engineer and Senior Engineer. He has a demonstrated history of working in the VLSI/Semiconductors industry and is well-versed in the latest technologies and trends in the field. Pawan holds a Bachelor's degree in Electrical Engineering from the prestigious Indian Institute of Technology, Bombay. During his time at IIT Bombay, he gained valuable experience and knowledge in the field of electrical engineering, which has helped him excel in his career. In addition to his technical expertise, Pawan is a skilled communicator and collaborator. He has a proven track record of working effectively with cross-functional teams and delivering high-quality results. He is also a quick learner and is always eager to take on new challenges and expand his skill set. Overall, Pawan Pareek is a highly skilled and experienced ASIC Design Verification Engineer with a passion for innovation and a commitment to excellence. His technical expertise, strong work ethic, and collaborative approach make him a valuable asset to any organization.
Education Overview
• iit bombay indian institute of technology bombay
Companies Overview
• qualcomm
• samsung
• cisco
• indian institute of technology
• gateforum
• arcelormittal
Experience Overview
10.7 Years
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Experience
Skills
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AISC
aisc
Algorithms
algorithms
Analog Circuit Design
analog circuit design
application specific integrated circuits
Application-Specific Integrated Circuits (ASI
ASIC
asic
ASIC Verification
asic verification
C
c
C++
c++
C++ Language
c++ language
Cadence Virtuoso
cadence virtuoso
Cadence Virtuoso Layout Editor
cadence virtuoso layout editor
Curve Fitting
curve fitting
Data Modeling
data modeling
Design
Digital Circuit Design
digital circuit design
Embedded Systems
embedded systems
field programmable gate arrays
Field-Programmable Gate Arrays (FPGA)
FPGA
fpga
Funcational Verification
funcational verification
Functional Verification
functional verification
Linux
linux
Matlab
matlab
ModelSim
modelsim
NGSPICE
ngspice
Optimization
optimization
Python
Senior Software Engineer
Software Development
software development
system verilog
SystemVerilog
systemverilog
UVM
uvm
Verilog
verilog
VHDL
vhdl
Xilinx
xilinx
Contact Details
Email (Verified)
pawXXXXXXXXXXXXXXXXXXXomMobile Number
+91XXXXXXXX24Education
iit bombay indian institute of technology bombay
2012 - 2014
Frequently asked questions
What company does Pawan Pareek work for?
Pawan Pareek works for google
What is Pawan Pareek role in his workplace?
Pawan Pareek's role in his workplace is asic design verification engineer
What is Pawan Pareek's tenure in his workplace?
Pawan Pareek's tenure in his workplace is 3.59 years
What is Pawan Pareek's total experience?
Pawan Pareek's total experience is 10.67 years
What is Pawan Pareek's LinkedIn profile?
What is Pawan Pareek's email address?
What is Pawan Pareek's phone/WhatsApp number?
What schools did Pawan Pareek attend?
Pawan Pareek has attended iit bombay indian institute of technology bombay
What companies has Pawan Pareek worked with?
Pawan Pareek has worked with google, qualcomm, qualcomm, samsung, samsung, cisco, indian institute of technology, gateforum, arcelormittal
What are some of Pawan Pareek's skills?
Pawan Pareek has skills in AISC, aisc, Algorithms, algorithms, Analog Circuit Design, analog circuit design and more.
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