About

Pawan Pareek is an experienced ASIC Design Verification Engineer with over 7 years of experience in IP/SOC Verification. He is skilled in System Verilog, UVM, and Python, and has experience in IP/Subsystem/SOC Design Verification. Currently, he works at Google as an ASIC Design Verification Engineer. Prior to his current role, Pawan worked at Qualcomm as a Senior Lead Engineer and Senior Engineer. He has a demonstrated history of working in the VLSI/Semiconductors industry and is well-versed in the latest technologies and trends in the field. Pawan holds a Bachelor's degree in Electrical Engineering from the prestigious Indian Institute of Technology, Bombay. During his time at IIT Bombay, he gained valuable experience and knowledge in the field of electrical engineering, which has helped him excel in his career. In addition to his technical expertise, Pawan is a skilled communicator and collaborator. He has a proven track record of working effectively with cross-functional teams and delivering high-quality results. He is also a quick learner and is always eager to take on new challenges and expand his skill set. Overall, Pawan Pareek is a highly skilled and experienced ASIC Design Verification Engineer with a passion for innovation and a commitment to excellence. His technical expertise, strong work ethic, and collaborative approach make him a valuable asset to any organization.