About

Pradeep Santdasani is a Senior ASIC Verification Engineer at Synopsys Inc with over 12 years of relevant experience. He is currently leading the PHY Serdes Testchip Verification Activity, responsible for the verification of PCIe6 and PAM-4 at a rate of 64 Gbps. Pradeep has developed an IP level UVM verification environment from scratch and has hands-on experience with Assertion, SV, UVM, and Emulation-friendly testbench. Pradeep specializes in System Verilog and UVM, and has extensive experience in verification activities. In his current role, he manages a team of three members and is responsible for the execution of Serdes Testchip Verification. Pradeep's past experience includes working at Mentor Graphics as an LMTS, where he verified the Display Port (DP 1.4) transactor and developed a behavioral model of Display Port Sink from scratch for the Verification of Display Port Source. He also developed an extensive assertion library for Display Protocol Compliance and worked on Constraint Random Verification using SV-UVM. Pradeep was also involved in the Mac-Link and Physical layer verification of Display Port 1.4 & eDP 1.4 and IP Verification on Veloce Emulation. Pradeep has also worked at Synopsys as an R&D Engineer 2, where he transferred with the whole team from STMicroelectronics to Synopsys. He worked on USB3 Designware Core (Subsystem) Verification. Pradeep holds an M.Tech degree in Communication Engineering from Nirma University, where he completed his studies in 2012. Overall, Pradeep is a highly skilled and experienced engineer with a strong background in ASIC Verification and UVM. He has a proven track record of leading teams and executing complex verification activities.