About

Prasanna Ramesh is a highly experienced Principal Design Engineer with over 9 years of relevant experience in the industry. He is currently working at Cadence Design Systems, where he is responsible for the design and development of high-speed samplers, 16Gbps PCIe Gen4 multi-tap DFE, 16Gbps GDDR6 Rx (loop unrolled) and clock distribution. Prior to joining Cadence Design Systems, Prasanna worked at Analog Devices as a Senior Design Engineer. During his tenure there, he designed and developed 12-bit ADC, 5GHz and 10GHz VCOs, phase detectors, frac-N PLL loop/phase noise modeling and lab correlation, TX architecture, two-point modulation for GFSK, 8-bit DAC, sigma delta dividers, external cap LDOs, and bandgap, among others. He also worked at Rambus as a Senior Member of the Technical Staff-II, where he designed and developed various circuits such as 13GHz LC oscillator for accurate Tpdm calibration, 2.4GHz clock receiver for minimum VT drift, 2.4GHz DFE-based data receiver, 7-bit phase interpolator for 800MHz clock, low VT drift fixed delay generation, DLL period jitter modeling, DCD calibration, RC oscillator, Tqsk adjust cell, Tqsk mechanism, VT drift evaluation for various blocks, 2.4GHz ring oscillator, bandgap, voltage regulators, offset cancellation through chopping, 13GHz TSPC-based dividers, etc. Prasanna holds a Master of Engineering degree in Microelectronic Systems and a Masters degree from IISc. He also has a Bachelor of Engineering degree in Electronics and Communication Engineering from the College of Engineering. He is well-versed in software engineering and has a strong tech stack. Overall, Prasanna Ramesh is a highly skilled and experienced Principal Design Engineer with a proven track record of designing and developing complex circuits. He is a valuable asset to any organization and is committed to delivering high-quality work.