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Prashanth Lingaiah
Principal Application Engineer at Cadence Design Systems
About
Prashanth Lingaiah is a highly skilled Principal Application Engineer at Cadence Design Systems, with over 12 years of experience in the field of electronics and communication engineering. He is currently working as a Trainee Engineer at qthink ic design, India, where he is responsible for designing and implementing netlist to GDS solutions for complex hierarchical modules in 14nm/20nm/28nm technologies. Prior to this, Prashanth worked as an Associate Engineer and Engineer at Qualcomm, where he gained extensive experience in netlist to GDS implementation of complex hierarchical modules. He has a proven track record of delivering high-quality solutions and driving successful projects from start to finish. Prashanth holds a Bachelor of Engineering degree in Electronics and Communication Engineering from Visvesvaraya Technological University. He is a highly motivated and dedicated professional who is passionate about staying up-to-date with the latest advancements in his field. He is a quick learner and has excellent problem-solving skills, which have helped him to successfully tackle complex challenges throughout his career. As a Principal Application Engineer, Prashanth is responsible for designing and implementing cutting-edge solutions that meet the needs of his clients. He is a natural leader who is able to work effectively with cross-functional teams to achieve project goals. He is known for his attention to detail, his ability to work under pressure, and his commitment to delivering results that exceed expectations. Overall, Prashanth Lingaiah is a highly skilled and experienced engineer who is passionate about his work and committed to delivering high-quality solutions. He is a valuable asset to any team and is always looking for new challenges and opportunities to grow and develop his skills.
Education Overview
• visvesvaraya technological university
Companies Overview
• cadence design systems
• qualcomm
• qthink ic design india
Experience Overview
13.1 Years
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ASIC
Clock Tree Synthesis
Design
Low-power Design
Physical Design
Static Timing Analysis
Contact Details
Email (Verified)
praXXXXXXXXXXXXXXXXXXXXXXXXXinMobile Number
988XXXXX09Education
visvesvaraya technological university
Bachelor of Engineering (BE)
2006 - 2010
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