About

Raghav Chawla is a Senior CPU PD Engineer at SiFive, with a passion for hardware-software co-optimization. He has over 4 years of relevant experience in the field of CPU Physical Design, having previously worked at Google and Intel. At Google, Raghav worked on next-gen mobile CPUs and achieved best in class PPA. He primarily focused on High Performance Core PD and sign-off. At Intel, he was responsible for the physical design aspects of the Image Processing Unit and Graphics IP, with a focus on optimization flows ranging from Floorplanning, Synthesis through GDS, and Static Timing Analysis. He collaborated with various teams for RTL optimization, timing signoff, and SoC integration, and owned Section level timing analysis and execution planning. Raghav holds a Bachelor of Technology degree in Electronics and Communications Engineering from the Indian Institute of Technology, Roorkee. He also completed his 12th grade from St. Kabir Senior Secondary School and his 10th Standard from Assumption Convent School. His technical expertise includes designer, Mobile, Image Processing, and Integration. Raghav is currently working on next-gen mobile phone CPUs at SiFive and is passionate about hardware-software co-optimization.