raghunath jetty
senior staff engineer
About
Raghunath Jetty is a highly experienced Senior Staff Engineer currently working at Qualcomm, where he has held various positions over the years. With a career spanning over 17 years, he has gained extensive knowledge and expertise in the industry. Raghunath's current role at Qualcomm involves leading a team of engineers in the development of cutting-edge technology solutions. He is responsible for designing and implementing software systems that are used in various applications. His work has contributed significantly to the success of Qualcomm, and he is highly respected within the organization for his technical skills and leadership abilities. Prior to his current position, Raghunath worked as a Staff Engineer and SMTS-Consultant at Qualcomm, where he gained valuable experience in software development and project management. He has also worked on several projects for other companies, which has given him a broad perspective on the industry. Raghunath holds a Bachelor's degree in Computer Science from Vishveshwaraiah Technological University and a Master's degree in Computer Science from Birla Institute of Technology and Science, Pilani. He also attended Oxford Polytechnic, where he completed a diploma in Computer Science. His educational background has provided him with a strong foundation in the field of computer science and has enabled him to excel in his career. Overall, Raghunath is a highly skilled and experienced engineer with a proven track record of success. He is passionate about his work and is always looking for ways to improve and innovate. His technical expertise, leadership abilities, and extensive experience make him a valuable asset to any organization.
Education
• bits pilani birla institute of technology and science
• visvesvaraya technological university
• oxford polytechnic
Companies
• qualcomm
• tech vulcan
• broadcom
• pmcsierra
• ibm
• cyient
• vxl infotech
Experience
18.1 Years
Experience
Skills
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application specific integrated circuits
asic
clock tree synthesis
design rule checking
drc
eda
floorplanning
ic
integrated circuit design
integrated circuits
logic synthesis
lvs
physical design
physical verification
place and route
power analysis
rtl design
signal integrity
soc
static timing analysis
system on a chip
systemverilog
tcl
timing closure
verilog
very large scale integration
vlsi
Contact Details
Email (Verified)
ragXXXXXXXXXXXXXXXXXXXXomMobile Number
+91XXXXXXXXXXEducation
bits pilani birla institute of technology and science
2010 - 2012
visvesvaraya technological university
2000 - 2004
oxford polytechnic
1997 - 2000
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