https://dream.weekday.works/redirectToHiringCopilotExtension/

gov.il

Venrock

Glynn Capital

Herald Investment Management

Entertainment Media Ventures

DPH Ventures

Dassault Developpement

De Incubator

Draper Athena

Gen 1 Capital

POKU CAPITAL

B Capital Fund

Osmium Global

Intel Nervana (earlier Nervana Systems) provides end to end solutions to enterprises for deep learning based development. Products include Python based open source deep learning framework "Neo", a full-stack SaaS platform called Nervana Cloud that enables businesses to create their own custom deep learning models and Nervana Hardware which is an AS

Provides end to end infrastructure for deep learning development

Application Engineer for ZeBu Emulator deployment 
- Responsible for successful bring-up of customer designs on ZeBu Emulation platform. 
- Successful integration and bring-up of transactors like AXI, SPI, I2C, MDIO, PCIe, Ethernet, etc and memory models like HBM2, DDR4 with customer design
- Enable customers to use novel solutions with ZeBu (like Virtual Machine with PCIe, Virtual IXIA with Ethernet) ensuring a flexible driver development platform.
- Implement debug strategies to narrow down debug window to the region of interest.

New Enterprise Associates

Morgenthaler

Western Technology Investment

VentureTech Alliance

Oak Investment Partners

Developer of AI and cloud-based EDA software for integrated circuit design and simulation. It provides electronic design automation, supplying the global electronics market with the software, IP, and services used in semiconductor design and manufacturing. It also offers an integrated portfolio of implementation, verification, IP, manufacturing, and FPGA solutions.

Developer of AI and cloud-based EDA software for integrated circuit design and simulation

Embedded Processors Group (SoC Design Verification)
Verification:
-	Understanding crucial use case scenarios and coming up with a verification strategy
-	Creating and reviewing test plans for various modules on SoC. Executing test plan through C based tests.
-	Ensuring 3rd party IP’s are properly integrated and all tests provided by vendor are run for integration and benchmarking.
-	Toggle coverage closure. Filling in gaps through directed testing as well as Jasper connectivity tests.
-	Gate level simulation and debug. Ensure team is enabled for the same by tackling setup issues.
-	Delivering and debugging test patterns to enable device qualification for mass production.
-	Communication with Arch/IP/PE teams to enable the above and tackling issues.

Team support activities:
-	Supporting linker scripts to enhance device performance
-	Enhancing build scripts for different device configurations
-	Provide support, debug and bring-up of modules on Emulation platforms (Palladium and Zebu) to help SW team develop drivers

Lightspeed Venture Partners

Ben Jen Holdings

Natural Bridges Ventures

Ben Franklin Technology Partners of Northeastern Pennsylvania

Manufacturer of semiconductor analog chips and embedded processors. It designs and develops semiconductor and computer technology including amplifiers, microcontrollers, motor drivers, data converters, sensors, power management and radio frequency ICs, and switches and multiplexers. It has applications in the automotive, consumer electronics, communication equipment, and industrial sectors.

Manufacturer of semiconductor analog chips and embedded processors

Wireless Transceiver Group.
Verification:
-	Verify functionality of DSP sub-blocks by simulating testbenches based on System-Verilog UVM at both RTL and Gate level. 
-	Performing FFT analysis at different stages of the pipeline to catch the block responsible for unintended amplification/attenuation of gain at tone frequency.
-	Analyzing coverage metrics to uncover holes in simulation and developing tests to fix them.

Design Responsibility:
-	Design of on-chip test pattern generators to verify functionality of Data Converters. Perform Lint Checks and IP Synthesis for timing and area estimate. 

Full Chip Initiatives:
-	Making sure the design is good to pass through different stages of design cycle e.g., Lint checking for RTL, Equivalence checking between RTL and Gates.
-	Architecting and Implementation of ECO/bug fixes in RTL. Re-Synthesizing the design and implement the changes into existing netlist using ECO cells and re-purposed gates.

Analog/Mixed Signal Verification:
-	Verification of SPI module taking IO Pads into consideration. Performance was measured across load on pads (capacitance) and operating voltage
-	Modeling oscillator in Verilog-AMS to improve simulation time for AMS simulations.

PIC microcontroller (8-bit) group.
Design Responsibility: 
-	Design of digital IP modules in Verilog and System Verilog. Optimization of IP modules for power and area.

Full Chip Initiatives:
-	Performed Full-Chip Power down simulations and streamlined the wake-up simulation flow by using the optimized configuration setting of the microcontroller.
-	Performed Lint checks for RTL and Equivalence Checking between RTL and Gates netlist.

Verification: 
-	Verification of digital IP modules and chip level interfaces by developing testbenches using Verilog and PIC assembly language. 
-	Analyzing coverage metrics to uncover holes in simulation and developing tests to fix them.

Design of chemical sensor based embedded systems to detect concentration and type of air/water borne pollutant.

Customer tailored applications deployed over the internet implementing SaaS (Software as a service) and advanced predictive modeling techniques.

PD Equalizer: Critical recording for any business or entity that needs to record incoming or outgoing calls for legal, quality control and training purposes. Provides call logging/Monitoring capabilities from a remote location as well as the server. 

Note-Link: Designed to take notes and link those notes directly to the exact point in time of the recording. Responsibility involved Requirement specification, Software Design as well as technical guidance towards technology use.

PLC and SCADA based Automated Control System: A 3-axes robotic system consisting of specialized axes to print thousands of probes on a standard glass microscope slide (1" x 3") for making DNA microarrays.