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Rakesh vummaneni
Sr.ASIC Engineer at NVIDIA
About
Rakesh Vummaneni is a seasoned Design Verification Engineer with over 12 years of experience in the field. He is currently employed at Facebook as a Design Verification Engineer, where he is responsible for ensuring the quality and functionality of the company's products. Prior to joining Facebook, Rakesh worked at Samsung as a Staff GPU Verification Engineer and later as a Senior GPU Verification Engineer. During his tenure at Samsung, he gained extensive experience in GPU design verification, which has been instrumental in his current role at Facebook. Rakesh's educational background includes a Bachelor's degree in Electronics and Communications Engineering from the National Institute of Technology Warangal (NIT Warangal) and a Master's degree in Electrical Engineering from Texas A&M University. He also attended Sri Venkateswara Bala Kuteer and Sri Chaitanya Junior College, Guntur, for his primary and secondary education, respectively. In terms of technical skills, Rakesh has expertise in Mobile technology and has worked on various projects related to it. He is highly proficient in using verification tools and methodologies, such as UVM, SystemVerilog, and Verilog. He is also well-versed in scripting languages like Perl and Python. Overall, Rakesh is a highly skilled Design Verification Engineer with a proven track record of success in the field. He is passionate about his work and is always looking for new challenges to enhance his skills and knowledge.
Education Overview
• texas am university
• nit warangal national institute of technology warangal
• sri venkateswara bala kuteer
Companies Overview
• samsung sarc acl
• qualcomm
• intel
• cirrus logic
• texas am university
• ntpc
Experience Overview
12.8 Years
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Experience
Skills
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algorithms
architecture
asic
automation
c
c++
computer architecture
Design
designer
digital ic design
electrical engineering
electronics
emulation
engineering
fpga
Frontend
Graphics
Hardware
ic
integrated circuit design
integrated circuits
labview
logic design
matlab
microprocessors
Mobile
perl
power plants
primavera p6
programming
rtl verification
scada
silicon validation
simulations
testing
verilog
very large scale integration
vhdl
vlsi
xilinx ise
Contact Details
Email (Verified)
rakXXXXXXXXXXXXXXXXXXXXXomMobile Number
+13XXXXXXX86Education
texas am university
Master's degree
2013 - 2015
nit warangal national institute of technology warangal
Btech
2004 - 2008
sri venkateswara bala kuteer
High school
1990 - 2002
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