About

Rakshita Joshi is an experienced Design Verification Engineer with a demonstrated 3 years history of working in the VLSI industry. She is skilled in SOC, IP, System Verilog, UVM, Verilog, AMBA APB, AHB, AXI, WDT, Timers, SPI, I2C, Coverage, Assertions, Testcases, Testplan, Debugging, Waveform analysis, RAL(Register Abstraction Layer), Synopsis tool: VCS, DVE, Verdi, Cadence tool: NCsim. She is a strong engineering professional with a B.Tech focused in Electronics and communication engineering from Motilal Nehru National Institute Of Technology (NIT Allahabad). Rakshita's technical skills include Hardware Description Languages like Verilog and System Verilog, Simulator like Synopsys VCS, DVE, Verdi, Xilinx ISim, Cadence NCSim, Protocols like AMBA APB, AHB, AXI, WDT, Timers, SPI, I2C, Verification like System Verilog, UVM, and Software Skills like Basic C. She is currently working as a Design Verification Engineer at Eximius Design and has relevant experience of 3 years in the VLSI industry. Prior to this, she has worked as a Summer Intern at DRDO Lab: Solid State Physics Laboratory, New Delhi, where she experimentally tested the desired characteristics of GaN High Electron Mobility Transfer devices. She has also worked as a Summer Trainee at CETPA, where she successfully completed a 6-week training and learned Verilog HDL. She also accomplished a project titled Digital Visitor Counter, which was hardware implemented. Rakshita has completed her B.Tech in Electronics and communication engineering from Motilal Nehru National Institute Of Technology (NIT Allahabad) in 2017. She has also completed her schooling from Fahaheel Al Watanieh Indian Private School (Delhi Public School), Kuwait, in Science in 2013. Apart from her work, Rakshita has also worked on GAN as a Research Scientist. She has a total of 6.20 years of relevant experience in the industry.