About

Rashmi Soni is a highly skilled VLSI professional with over 9 years of experience in RTL Design & Verification, Acceleration VIP development for Emulation platform. Currently working as a Principal Software Engineer in Cadence Design System Inc. Bengaluru, Rashmi has a strong background in creating Synthesizable RTL components from scratch and experience in micro-architecting design straight from standard specification. She is equipped with hands-on experience in Hardware Verification language and Hardware Design language and possesses good experience on test bench development varied interface based on distinct Verification Methodologies. Rashmi has worked extensively with EDA tools and has strong knowledge and hands-on experience on plenty of protocols like USB2.0, USB3.0, PCI Express, HDMI 1.4, HDMI2.0, DP 1.4, PCS-200G/400G, PCS-100G/50G, etc. Currently, she is working on the development of HDMI2.1 Acceleration VIP for the palladium platform. She is highly versatile and experienced in adapting and implementing the latest technologies. Rashmi is able to work adaptively in a team as well as an individual contributor. She possesses strong communication skills and is proficient in cross-geography customer interaction and cross-geography team collaborations. Rashmi's past experience includes working as a Lead Software Engineer and MTS at Cadence Design Systems. As a Lead Software Engineer, she was responsible for creating Synthesizable RTL components for Accelerated VIP and worked on multiple high-speed serial protocols like USB2.0, HDMI, Ethernet PCS/PMA, Display Port. She was equipped with RTL writing skills required for the Emulation platform to ensure minimum consumption of Gate Area & Step Count. Rashmi also mentored & managed a team of two freshers and was involved in customer interaction and multiple team collaboration for product developments/deliverables. As an Individual contributor, she added emulation utilities to AVIPs to enhance testing capability and debug-ability. Rashmi has relevant experience of 12.36 years and has completed trainings on System Verilog Verification by Synopsys Inc. and on UVM by Synopsys Inc. & Cadence Design System. Her tech stack includes Software Engineer, test, and Senior Software Engineer.