About

Rishabh Bhargav is a Design Verification Engineer at Google with over 4.87 years of relevant experience in the field. He has expertise in creating verification plans, developing test benches, generating constrained random stimuli, feature verification and debug, functional and code coverage analysis/closure for both SoC DV and IP DV. In addition to this, he is also an expert in performing SoC checks/IP verification using formal techniques. Rishabh is well-versed in programming languages such as C/HDL (Verilog) and scripting languages like Perl and TCL. He has worked with various tools such as NCSIM, IEV, JG (FPV, CSR), vManager, and vPlanner. Prior to joining Google, Rishabh worked as a Digital Engineer at Texas Instruments, where he was responsible for DV engineering for C2000 Microcontrollers. He also worked as an intern at Nvidia in the performance architecture team for memory subsystems. Rishabh holds a Master of Engineering (M.Eng.) degree in Microelectronics Engineering from Birla Institute of Technology and Science, Pilani, and a Bachelor of Technology (B.Tech) in Electrical, Electronics and Communications Engineering from National Institute of Technology, Srinagar. He completed his schooling from St. Thomas School, Indirapuram, Ghaziabad. Overall, Rishabh is a skilled Design Verification Engineer with expertise in creating verification plans, developing test benches, and generating constrained random stimuli for both SoC DV and IP DV. He is highly proficient in programming and scripting languages and has worked with various tools to deliver quality results.