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Rishabh Keshari
Sr. DV Engineer at Qualcomm || Ex-Intel || ASU, BITS Pilani
About
Rishabh Keshari is a highly skilled Sr. DV Engineer at Qualcomm, San Diego, CA, with over 8 years of experience in the semiconductor industry. He specializes in Video and Machine Learning IP DV Engineering, with a strong background in Graphics Design Verification, DFx DV Engineering, and DFT and Automation. Rishabh has worked at Intel Corporation, Folsom, CA, and Chandler, AZ, where he was responsible for the verification of Power Management Unit for Graphics Engine at cluster level, developing SV-based verification components and test cases for HVM Reset flow at IP level, and owning TAP to Sideband protocol converter unit Verification. He has also worked at ST Microelectronics, where he was responsible for FE Memory BIST verification and Verilog Memory behavioral model development. Rishabh holds an MS in Electrical Engineering from Arizona State University, with a CGPA of 4/4, and a bachelor of engineering (B.E.) degree in Electrical and Electronic Engineering from BITS-Pilani. He has also completed a Master of Science in Chemistry from BITS-Pilani. Rishabh's technical skills include ML, designer, Research Scientist, and test. He is a highly motivated and dedicated professional with a passion for problem-solving and a strong ability to work collaboratively with cross-functional teams.
Education Overview
• arizona state university
• bits pilani birla institute of technology and science
Companies Overview
• qualcomm
• intel
• hourglass research
• masamb electronics systems
• stmicroelectronics
• indian institute of technology bombay
Experience Overview
9.6 Years
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Experience
Video and Machine Learning HW DV Engineer
qualcomm | San Diego, California, United States
2020 - Present
Skills
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Assertion Based Verification
Automation
C
C++
Code Coverage
Design
designer
DFT
Electrical Engineering
Graphics
Hardware
IP
Logic Design
Machine Learning (ML)
Manufacturing
Perl
Power Management
Research
Research Scientist
RTL design
SAN
soc
Static Timing Analysis
SVA
SystemVerilog
TCL
test
test cases
Universal Verification Methodology (UVM)
Verdi
Verilog
Contact Details
Email (Verified)
kesXXXXXXXXXXXXXXXXXXXXomMobile Number
+91XXXXXXXXXXEducation
arizona state university
Master of Science (M.S.)
2014 - 2015
bits pilani birla institute of technology and science
Bachelor of Engineering (BE)
2008 - 2013
bits pilani birla institute of technology and science
Master of Science (MSc)
2008 - 2013
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