About

Sagar Mishra is a Verification IP Engineer at Cadence Design Systems with over 2 years of relevant experience. He is skilled in Advanced Digital, Verilog, SV, Functional Coverage, Assertions, and UVM. Sagar completed his Master of Technology in VLSI Design from c-dac in 2020. Prior to that, he obtained a Bachelor of Technology in Electronics and Communications Engineering from rtu in 2018. He also holds a Certification in VHDL from c-dac, which he completed in 2017. Before joining Cadence Design Systems, Sagar worked as a Verification Engineer at AMD for 1.5 years. He was responsible for developing test benches and running simulations for various AMD products. As a Verification IP Engineer at Cadence Design Systems, Sagar is responsible for developing and verifying various protocols such as PCIe, Ethernet, and AMBA. He also works on developing and maintaining verification IP for these protocols. Sagar is a highly motivated and dedicated individual with a passion for his work. He is constantly seeking new challenges and opportunities to learn and grow in his field. With his strong technical skills and experience, he is a valuable asset to any team.