https://dream.weekday.works/redirectToHiringCopilotExtension/

gov.il

Venrock

Glynn Capital

Herald Investment Management

Entertainment Media Ventures

DPH Ventures

Dassault Developpement

De Incubator

Draper Athena

Gen 1 Capital

POKU CAPITAL

B Capital Fund

Osmium Global

Intel Nervana (earlier Nervana Systems) provides end to end solutions to enterprises for deep learning based development. Products include Python based open source deep learning framework "Neo", a full-stack SaaS platform called Nervana Cloud that enables businesses to create their own custom deep learning models and Nervana Hardware which is an AS

Provides end to end infrastructure for deep learning development

Matrix Partners

Crosslink Capital

InterWest Partners

Silver Creek Ventures

Point Financial

OVP Venture Partners

Gaorong Capital

Kleiner Perkins

SquareOne

Provider of programmable logic devices. Its solutions include advanced integrated circuits, software design tools, predefined system functions are delivered as intellectual property cores, design services, customer training, field engineering, and technical support services. Its FPGAs and embedded solutions are based on cloud computing and machine learning.

Changed my role from an EDA/emulation engineer to   Kernel acceleration engineer. In this new role responsible for adding new accelerated kernels to vitis library. 
Till now mainly worked on lossless compression and decompression acceleration (gzip/zlib/zstd). Worked on both side of the world, from creating efficient kernel to writing optimised x86 code to use this accelerated kernels.
Checkout our libraries here 
https://github.com/Xilinx/Vitis_Libraries/tree/master/data_compression

Current role EDA/emulation engineer. Current responsibility is to speed up the simulation for vitis flow, multiple simulator support and SystemC automation in vivado tool chain.
Under this role worked on following stuff
1. Bringing in new Cycle accurate and TLM based SystemC simulation models to replace most of the RTL based models from the system for faster simulation.
2. Worked on tool automation to bring in support for multiple simulators for SystemC in vivado
3. Responsible for creating a base library for SystemC models(xTLM). This library provide all the basic support and utilities to create cycle accurate TLM models with full AMBA AXI support to help these model work with other RTL/SystemC models in the system
4. Vivado tool automation to automatically generate netlist for the Hybrid systems(RTL/SystemC together in a system)

Responsibilities 
~ To modify and develop the features present in Sysgen by using C++, Tcl and Matlab.

Experienced gained
-- Development using C++, Tcl
-- Tools: Matlab, Vivado, ISE
-- Languages: Verilog, VHDL
-- Management: Time Management & Team Management.

I got hands on training on System Verilog, Verilog and Tcl Scripting through professionals who had been in the EDA/ASIC/Embedded industry for more than 10 years in companies such as Cadence Design Systems & Patni Computers

DKOP Labs Pvt. Ltd. ( Earlier DesignKOP Labs ) is a Research and Training company in VLSI Design, Embedded Systems & Software Development. It is founded by a team of highly experienced and qualified Semiconductor & EDA Industry Professionals. DKOP Labs Finishing School, the Training Division, conducts various industrial training programs in VLSI Design, Embedded Technology & Software Development.