About

Sankalp Jain is an experienced ASIC Design Engineer at Apple with a strong background in digital design engineering and analytical skills. With over 4 years of experience in ASIC/VLSI design, verification, and automation using scripting, Sankalp has become proficient in the field of ASIC/VLSI Design. His technical expertise includes front and back-end ASIC design flow, RTL design, floor-planning, synthesis, APR, timing closure, and working with layout engineers to fix DRC/LVS issues. He has also successfully debugged complex issues for timing closure and in ICC/Primetime. Sankalp's experience includes working as a Sr. Design Engineer and Design Engineer 2 at Microchip Technology Inc. before joining Apple. He has also completed his Master of Science (M.S.) in Electrical and Electronics Engineering from Arizona State University and his Bachelor of Technology (B.Tech.) in Electrical, Electronics, and Communications Engineering from West Bengal University of Technology. Sankalp's research focus has been on scheduling algorithms for Asymmetric Multi-Core processors for performance and energy optimization. He has experience in working with Qualcomm Snapdragon 800 asymmetric processor and Samsung Exynos 5410 heterogeneous processor. Sankalp is a quick learner and eager to gain more experience and learn new skills. His technical skills include Encounter, RTL, Primetime, ICC, DC Complier, HSpice, Cadence Virtuoso XL, Verilog, System Verilog, C, C++, JAVA, TCL, Perl, and Modelsim. He is also proficient in backend development, Java, and research science. With 8.71 years of relevant experience, Sankalp is a valuable asset to any team and is always looking for new challenges to enhance his skills.