About

Saurabh Poswal is a highly skilled Software Engineer with over 4 years of experience in the verification domain. Currently, he is working at Cadence Design Systems as a Software Engineer 2. Saurabh's expertise lies in developing and implementing software solutions to improve the efficiency and effectiveness of the verification process. In his current role at Cadence Design Systems, Saurabh is responsible for designing and developing verification IPs for complex SoCs. He has a deep understanding of verification methodologies such as UVM and SystemVerilog. Saurabh is also proficient in scripting languages like Perl and Python, which he uses to automate various tasks in the verification process. Before joining Cadence Design Systems, Saurabh worked as a Verification Engineer at Agnisys, where he was responsible for developing and verifying hardware description languages. He has a Bachelor of Technology degree in Electronics and Instrumentation from AKTU. Saurabh's technical skills include software engineering, UVM, SystemVerilog, scripting languages, and hardware description languages. He is a quick learner and has a strong problem-solving ability, which allows him to come up with innovative solutions to complex problems. Overall, Saurabh Poswal is a talented Software Engineer with a passion for developing cutting-edge solutions in the verification domain. His technical expertise, coupled with his problem-solving ability, makes him a valuable asset to any organization.