About

Saurabh Sharma is a highly experienced Senior Engineering Manager at Siemens Digital Industries Software. With over 16 years of relevant experience, he is a System Verilog specialist with expertise in developing VIP environment using UVM, OVM, AVM, VMM, verilog verification frameworks for AMBA AXI, AHB, APB, ACE, I2C, MIPI CSI2 PCIe Verification IP, with a focus on Functional Coverage based Constrained Random Testing. Saurabh has actively contributed to a number of chip tapeouts as a member of the SoC verification team, where his responsibilities included coding C/Verilog/System Verilog test cases, assertions based connectivity checks using IFV, debugging bugs, and code coverages. He has also contributed to a number of chip tapeouts as a member of the SoC integration team, where he was responsible for RTL coding, HAL linting, CDC, and fixing ECOs. In terms of his specialties, Saurabh has experience working with repositories such as CVS, VSS, Clearcase, and Designsych. He is well-versed in verification frameworks such as AVM, VMM, OVM, and UVM, and has experience working with tools such as Mentor Graphics ModelSim and QuestaSim, Synopsys VCS, Virsim, and DVE, Cadence NC Verilog, SimVision, and Incisive, and Novas Verdi and Debussy. He is also familiar with popular standards and buses such as DDR3, AHB2, AXI4, AXI3, APB4, ACE, SATA AHCI, PCIe, I2C, MIPI CSI2, NVMe, and CHI. Prior to joining Siemens, Saurabh worked as an Engineering Manager at Mentor Graphics and as a Lead Engineer at Truechip Solutions, where he specialized in Verification IP. He holds a Bachelor's degree in Technology in Electronics and Communication from GGSIPU. Overall, Saurabh is a highly skilled and experienced Senior Engineering Manager with a strong background in System Verilog and SoC verification and integration.