About

Shankar Prasad Agrawal is an experienced RTL Design Engineer, currently working at Google. He has a strong background in SoC and IP design, sub-system design, and integration. Shankar is well-versed in various design rule checks such as CDC, SPY-DFT, SPY-Lint, DCLINT, and SFR test at both IP and chip level. He is also proficient in GLS setup and run, UPF integration, low power strategy, and checks. Shankar has expertise in SoC environment and database management, and he provides support to the DV team. Shankar has knowledge of Coresight SoC-600 and LPDDR4 Spec, GPU, AMBA protocols, and Interconnects. He has experience in defining architecture and micro-architecture features, writing specifications, and understanding implementation tradeoffs such as performance, power, and frequency. Shankar has also contributed to the GPU block level design document, such as interface protocol, block diagrams, transaction level flow, control registers, pipelines, etc. He is proficient in RTL development process, coding, and debug in Verilog/SystemVerilog, function/performance simulation debug, and Lint/CDC/FeV/PowerIntent checks. Shankar has contributed to the SoC level integration and participated in synthesis, timing/power closure, and silicon bring-up. He has also participated in the test plan and coverage analysis of the block and SOC-level verification. Before joining Google, Shankar worked at Samsung as a Staff Engineer and Associate Staff Engineer. Shankar holds a Master of Technology (M.Tech.) degree in Microelectronics & VLSI from the Indian Institute of Technology, Bombay, and a Bachelor of Technology (B.Tech.) degree in Electrical and Electronics Engineering from the Indian Institute of Technology, Indore. He has relevant experience of 5.63 years and is proficient in Integration, test, and Mobile tech stack.