About

Shivam Kaushal is an experienced engineering manager at Intel Corporation with a focus on physical design engineering. With over 9 years of relevant experience, Shivam has developed a strong skill set in ASIC Physical Design, RTL to GDSII implementation, and Hardware Design Tools. Shivam's specialties include ASIIC Physical Design RTL2GDSII (Synthesis, Constraint Debug, Floorplanning, Congestion Reduction, Die-Size Reduction, Power routing/analysis and fixes, CTS, Routing, STA, ECO Fixes.), as well as proficiency in Synopsys, Cadence IC Design tool sets, Primetime, Calibre & Star-RC. He also has experience in scripting tools such as Perl and Tcl, and hardware languages such as Verilog HDL. In his current role as Staff Engineer/Engineering Manager at Intel, Shivam is leading Ethernet IP hardening and managing 28 parts of different complexities for the Meteor Lake project. He has also held previous positions at Intel as a Senior Lead Physical Design Engineer and Senior Design Engineer, where he was responsible for high complexity block implementation from RTL to GDSII, and block level implementation from RTL to GDSII, respectively. Shivam holds a Bachelor of Technology (BTech) in Electronics and Communications Engineering from the Indian Institute of Information Technology (IIIT), where he graduated in 2014. He also attended JNSVM Inter College, where he studied PCM from 2006 to 2007. Overall, Shivam is a quick learner and a good team player who consistently delivers on assigned tasks. He has a proven track record of resolving issues proactively and providing value-add to projects by reducing cycle-time and developing efficient solutions.