About

Shivangi Dixit is an experienced R&D Engineer with over 3 years of experience in the EDA domain. She is currently working as an R&D Engineer II at Synopsys, where she is responsible for the Power Analysis module of IC Compiler II (ICC2). Shivangi has a postgraduate degree (MTech) specialized in Information Security from Indira Gandhi Delhi Technical University for Women, and a Bachelor of Technology (B.Tech) in Computer Science and Engineering from Maharaja Agrasen Institute of Technology. With a strong reasoning aptitude and proficiency in C/C++, Shivangi has worked on various FPGA Synthesis tools like Xilinx Vivado, Mentor Precision RTL Synthesis, and Power Analysis tools like ICC2 and PrimeTime PX. She is experienced in using tools like Verilog, Linux, TCL, GDB, Perforce (GUI and command-line), Valgrind, and coverity fixes. Shivangi has previously worked as an R&D Engineer I at Synopsys and as a Software R&D Intern at Mentor Graphics. At Mentor Graphics, she designed an automated mechanism to extract conditional timing models in FPGAs using Perl scripting language and Verilog (HDL) to create various instantiated test cases. She mapped different multiplier testbench to DSP blocks and analyzed the generated timing reports. Shivangi's education history includes a Master of Technology (M.Tech) in Information Security Management from Indira Gandhi Delhi Technical University for Women and a Bachelor of Technology (B.Tech) in Computer Science and Engineering from Maharaja Agrasen Institute of Technology. She also has a background in Science Stream from Swiss Cottage School and Salwan Public School - India. Shivangi is a skilled Software Engineer with a relevant experience of 4.19 years. She is passionate about broadening her knowledge space in the field of Software Development and is always looking for new challenges to grow her skills.