About

Shubham Agarwal is a Principal VIP R&D Engineer at Cadence Design Systems, with over 7 years of experience in the field of VLSI verification. He has spent 5 years at Cadence Design Systems as a Lead VIP R&D Engineer, where he has gained proficiency in languages such as C, System Verilog, and UVM, and tools like Xcelium and IMC. He has also worked on various protocols such as Ethernet (up to 800G speed), FlexE, PHY Timestamping, and 5G Networking. Prior to his current role, Shubham worked for 2 years and 10 months as a VLSI Verification Engineer at WIPRO Technologies. During his time there, he gained expertise in languages such as System Verilog, UVM, VHDL, and Verilog, and tools like Questa Sim, VCS, and IMC. He has also worked on protocols such as AXI and PCIE (Transaction Layer) and has experience in Perl scripting. Shubham holds a Master's degree in Microelectronics from Birla Institute of Technology and Science, Pilani, and a PG-Diploma in VLSI Design from CDAC, ACTS Pune. He also has a Bachelor's degree in Electronic and Communications Engineering Technology from Rajkumar Goel Institute of Technology, Ghaziabad, and completed his Intermediate education in Mathematics from Saraswati Shishu Mandir Senior Secondary School, Gorakhpur. Shubham is skilled in software engineering and has relevant experience of 4.87 years. He is a highly motivated individual with a passion for VLSI verification and a proven track record of delivering high-quality results.