Shyna Dmello
FPGA Engineer at Rakuten Symphony
About
Shyna Dmello is an experienced FPGA Engineer, currently working at Rakuten Symphony. With a career spanning over 8 years, Shyna has gained extensive knowledge and expertise in hardware design and system engineering. In her current role at AltioStar, Shyna is responsible for designing and implementing FPGA-based solutions for Rakuten Symphony's advanced communication systems. She works closely with cross-functional teams to ensure the successful integration of FPGA solutions into the overall system architecture. Prior to joining AltioStar, Shyna worked as a Senior Engineer in Hardware Design at Mistral, where she was responsible for designing and developing complex hardware solutions for various clients in the telecommunications industry. She also worked as a Senior System Engineer at Accord Software & Systems, where she was involved in the design and development of system-level solutions for clients in the aerospace and defense industries. Shyna holds a Bachelor of Engineering degree from the Mangalore Institute of Engineering & Technology, with a focus on FPGA design and implementation. Her education and experience have equipped her with a deep understanding of hardware design, system engineering, and FPGA-based solutions. With 8.69 years of relevant experience, Shyna is a highly skilled and knowledgeable FPGA Engineer, capable of delivering complex solutions to meet the needs of her clients. She is committed to staying up-to-date with the latest industry trends and technologies, and is always seeking new opportunities to expand her knowledge and expertise.
Education
• mangalore institute of technology engineering
• pompei college aikala india
Companies
• altiostar
• mistral
• accord software systems
Experience
7.8 Years
Experience
Skills
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4G
5G New Radio (NR)
Altera
Altera Quartus
asic
AXI
Chipscope
Debugging
Design
Digital Logic
Ethernet
Field-Programmable Gate Arrays (FPGA)
FPGA
Hardware
Hardware Architecture
Hardware Description Language
JESD204B
Logic Analyzer
Logic Design
Logic Gates
MATLAB
ModelSim
O-RAN
PTP
RTL Coding
RTL Design
rtl design
RTL Development
Semiconductor Engineering
SerDes
Static Timing Analysis
Timing
Timing Closure
Transceivers
Verilog
VHDL
Xilinx
Xilinx Vivado
Contact Details
Email (Verified)
shyXXXXXXXXXXXXXomMobile Number
+91XXXXXXXXXXEducation
mangalore institute of technology engineering
BE - Bachelor of Engineering
2010 - 2014
pompei college aikala india
Puc
2008 - 2010
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