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srinivas dharmavaram
senior staff engineer
About
Srinivas Dharmavaram is a highly experienced Senior Staff Engineer with over 15 years of relevant experience in the technology industry. Currently working at Qualcomm, Srinivas has held the same position at Qualcomm Technologies in the past. He has also worked as a Principal Application Engineer at Cadence Design Systems. Srinivas has a strong educational background, having completed his Bachelor's degree in Electronics and Communication Engineering from Jawaharlal Nehru Technological University, Anantapur in 2001. He then pursued his Master's degree in Electrical and Computer Engineering from Michigan State University, graduating in 2004. Srinivas continued his academic pursuits and completed his PhD in Electrical and Computer Engineering from Michigan State University in 2018. Throughout his career, Srinivas has demonstrated his expertise in various areas, including system architecture, design and verification, and software development. He has a proven track record of delivering successful projects and has been recognized for his contributions to the industry. As a Senior Staff Engineer, Srinivas is responsible for leading technical teams and driving innovation in his field. He is highly skilled in problem-solving and has a keen eye for detail. Srinivas is a valuable asset to any organization and is committed to delivering high-quality work. In his free time, Srinivas enjoys reading and staying up-to-date on the latest technological advancements. He is also passionate about giving back to the community and regularly volunteers his time to various charitable organizations.
Education Overview
• michigan state university
• jawaharlal nehru technological university anantapur
Companies Overview
• qualcomm technologies
• cadence design systems
• qualcomm
• analog devices
• pmcsierra
• nxp semiconductors
• wipro
Experience Overview
16.5 Years
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Experience
principal application engineer
cadence design systems | san jose, california, united states
2015 - 2017
Skills
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asic
atoptech aprisa
cadence
caliber drc/lvs
clock tree synthesis
drc
floorplanning
logic synthesis
magma
physical design
physical verification
primetime
rtl design
soc
static timing analysis
synopsys tools
tcl
timing closure
verilog
vlsi
Contact Details
Email (Verified)
nivXXXXXXXXXXXomMobile Number
+91XXXXXXXXXXEducation
michigan state university
2015 - 2018
michigan state university
2001 - 2004
jawaharlal nehru technological university anantapur
1997 - 2001
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