About

Subham Gola is a highly skilled PDK Runset Developer at Intel Corporation with a passion for physical verification and layout design. With a Master of Technology in VLSI Design from VIT Vellore, Subham has a strong academic background that has equipped him with the knowledge and skills to excel in his current role. He has a CGPA of 8.6 and has gained invaluable experience working with a range of tools and technologies. Subham has a solid understanding of TCL scripting and has worked on a variety of tools, including Calibre DESIGNrev, CalibreRVE, Synopsis IC validator, and Cadence Virtuoso Tool. He also has knowledge of CalibreDRV scripting and SVRF scripting, which he has used to great effect in his work on layout design on CalibreDRV and Cadence Virtuoso layout editor tools. Subham's experience in physical verification has been honed through his work at Siemens EDA (formerly Mentor Graphics), where he was an Application Engineer Intern. In addition to his work at Intel Corporation and Siemens EDA, Subham has completed two projects during his training period at T.I.M.E., where he learned about the Internet of Things (IoT) and completed projects on wireless temperature monitoring systems and mobile-controlled LED light systems using Arduino boards, Bluetooth modules, and LED. Subham's education history includes a Bachelor of Technology in Electronics and Communications Engineering from G.B. Pant Govt. Engineering College and a Higher Secondary School education in Mathematics and Computer Science from Kendriya Vidyalaya. Subham's technical skills extend beyond his work in physical verification, and he has experience in mobile development. With 1.43 years of relevant experience, Subham is a highly skilled and motivated professional who is always looking for new opportunities to learn and grow.