About

Sudipta Ranjan is a Design and Verification Engineer with a strong problem-solving ability and over 3.86 years of relevant experience. Currently, he is working as a Senior Verification Engineer at Happiest Minds. Sudipta has expertise in Testbench development using System Verilog and UVM. He is a skilled engineer who has worked on the Physical Layer of Pcie Gen 1/2/3/4 and Register configuration, Monitor Integration on Subsystem Level TB at Logic Fruit Technologies. He has also worked as a Member of Technical Staff at Smart IOPS, where he was responsible for performing Design and Verification and Digital IP integration of different blocks. Sudipta has completed his Bachelor of Engineering in Electronics and Instrumentation from Bangalore Institute of Technology in 2018. He also holds a High School degree in Physics, Chemistry, and Mathematics from Sree Ayyappa Public School, Bokaro. Apart from his technical skills, Sudipta has experience in Mobile, Research Scientist, Integration, and Software Engineer. He is a dedicated and hardworking professional who is always willing to learn and adapt to new technologies.