About

Sujith Hiremath is an experienced Staff Engineer at Qualcomm with over 12 years of relevant experience in the field of verification of SOCs, Memory Subsystems, SERDES, and Hardware Security IPs. He has worked on designs for Crypto, Encrypted memory sub-system, PCIe Gen3, SATA 3, USB 3/3.1, DDR3/4, LPDDR3, and HBM among other protocols. Currently, Sujith is responsible for the verification of Hardware Security IPs at Qualcomm. In his previous role as a Senior Technical Analyst at UST, he was involved in the verification of HSIO subsystem for PCH Soc and was also responsible for the verification of PCIe and SATA IP stack. At Rambus, as a Senior Member Technical Staff, he worked on the functional verification of Smart Data Accelerator SOC involving various IPs such as PCIe Controller, DMA, NoC, Nios processor, and DDR3 memory sub-system. He also worked on the hardware validation of SOC using Lecroy PCIe protocol analyzers and generators. Sujith has a Bachelor of Engineering degree in Electronics and Communication from PES and has completed his schooling from National College Jayanagar and Carmel School. He has also published a paper at Design Con 2017 on the re-use of verification tests for the generation of validation vectors and firmware code. Sujith's technical skills include Software Engineering and Testing. He has experience in developing re-usable verification components for SATA3, DDR3, AXI, APB, I2C, JTAG, and has piloted the effort to migrate regression tools from NCVerilog to Questasim. He has also automated the exercise via Perl scripts to conform to Rambus Verification Environment flow. Overall, Sujith is a highly skilled and experienced engineer with expertise in verification and validation of complex hardware designs. His technical skills, combined with his experience, make him a valuable asset to any organization.