About

Sukriti Khanna is a highly skilled STA Engineer at Apple, with a strong background in Static Timing Analysis (STA) and experience in technologies like Statistical On-Chip Variation (SOCV), Graph & Path Based Analysis (GBA/PBA), Timing Constraints, Hierarchical Timing Flows, and Functional Validation of Engineering Change Order (ECOs). She is currently pursuing her Master's degree in Electrical and Computer Engineering, majoring in IC VLSI at the University of Michigan. With over 4 years of relevant experience, Sukriti has previously worked at Cadence as a Product Validation Engineer II, Static Timing Analysis, where she was responsible for the functional validation of Hierarchical Timing Flows, Distributed STA, Multi-mode Multi-corner timing analysis, and ECOs for meeting timing signoff. She has also worked as a Static Timing Analysis Intern at Apple. Sukriti's exceptional academic background includes a Bachelor of Technology degree in Electrical and Electronics Engineering from DTU and her current Master's program at the University of Michigan. She has demonstrated her expertise in the field of STA by developing and functionally validating features for TEMPUS at Cadence. As a SOC STA Engineer at Apple, Sukriti is responsible for ensuring the timing signoff of Apple's SOC designs. She leverages her expertise in STA to develop and execute timing methodologies, analyze timing constraints, and perform STA on various SOC blocks. She also collaborates with cross-functional teams to debug and resolve STA-related issues. Sukriti's passion for STA and her strong technical skills make her an asset to any team she works with. She is a highly motivated individual who is always eager to learn and grow in her field.