About

Sulabh Khare is a highly skilled Staff Engineer at Siemens EDA with over 16 years of relevant experience in the industry. He possesses a deep understanding of C, C++, Algorithms, Data Structures, and EDA software, making him an expert in the field of Electronic Design Automation (EDA). Sulabh is well-versed in Object-Oriented Design and Analysis, Software Product Flow Architectures, Front-End Compilers (VHDL, Verilog, System Verilog), and RTL Synthesis. He is also proficient in Assertion-Based Verification and SDC (Synopsys Design Constraints), with a strong grasp of Clock Domain Crossing. Currently, Sulabh holds the position of Principal Engineer at Siemens, where he is responsible for developing and implementing complex software solutions. Prior to this, he worked as a Staff Engineer at Mentor Graphics, where he honed his skills and gained valuable experience in the industry. Sulabh has a Master's degree in Microelectronics and VLSI Design from the Indian Institute of Technology, Kharagpur, and a Bachelor of Engineering degree in Electrical Electronics and Communications Engineering from Shri Vaishnav Institute of Technology and Science, Indore. With his extensive knowledge and expertise, Sulabh is a valuable asset to any organization. He is a highly motivated individual who is passionate about his work and always strives for excellence. His ability to work effectively in a team and his strong communication skills make him an excellent collaborator and leader. Sulabh's dedication to his work and his commitment to delivering high-quality results make him an invaluable member of any team.