About

Sumit Gautam is a highly skilled Physical Design Engineer with over 5 years of experience in the field. He has worked on a range of projects, including mobile SOC/modem (Heliox), DDR (HBM), and SERDES IPs. Sumit has experience in 5nm, 7nm, 10nm, 14nm, 28 nm, and below technology nodes and has worked with TSMC and Samsung foundries. Sumit has won the All India Mentor Graphics Design Contest in 2014 and has experience in RTL to GDSII implementation and Physical Verification. He is proficient in the Physical Design Flow on ICC Tool, including Floor Planning, Placement, Clock Tree Synthesis (CTS), Static Timing Analysis (STA), Routing, Congestion, and Timing Verification. Sumit also has experience in ECO APR flow and Physical Verification (DRC, LVS, ERC, Antenna, and LEC) and Timing library Profiling. Sumit has a strong understanding of Timing and Design constraints (SDC) and Library Profiling and has knowledge of all types of Timing and Delay model (NLDM and CCS). Currently, Sumit is working as a Senior Lead Engineer at Qualcomm, where he is responsible for handling individual projects with OS. Sumit's past experience includes working as a Staff Engineer and Associate Staff Engineer at Samsung. He has a Master of Technology (M.Tech.) in Microelectronics and VLSI from IIIT and a Bachelor's degree in Electronics and Communication Engineering from the Indian Institute of Information Technology, Design, and Manufacturing, Jabalpur. Sumit is a Senior Software Engineer with expertise in Mobile and Design. With 8.12 years of relevant experience, he is a valuable addition to any team in the Physical Design Engineering field.