About

Surbhi Agarwal is a seasoned Senior Engineer DFT at Marvell Technology with over 5 years of relevant experience in the industry. She is a skilled DFT engineer with a strong background in VLSI chip designing and verification methodologies. Surbhi has worked with several reputable companies in the past, including Synopsys and Skandysys, where she held positions as a Design Group Engineer and DFT Engineer, respectively. Her expertise in these roles has equipped her with a wealth of knowledge and experience in the field. In terms of education, Surbhi completed her Bachelor of Technology in Electrical, Electronics, and Communications Engineering from MCKV Institute of Engineering in 2018. Prior to that, she also underwent training in VLSI chip designing and verification methodologies at Maven Silicon. As a Senior Engineer at Marvell Technology, Surbhi is responsible for overseeing the design-for-test (DFT) process for complex SoC designs. She has a deep understanding of DFT methodologies and techniques, and her expertise has been instrumental in ensuring the quality and reliability of Marvell's products. Overall, Surbhi is a highly skilled and experienced DFT engineer with a passion for delivering high-quality results. Her dedication to her work and her ability to work collaboratively with others make her a valuable asset to any team.