About

Swapnil Patil is an enthusiastic engineer with a passion for innovation and improving existing technology in Electronics and Telecommunication engineering. He is currently working as an FPGA/RTL Design Engineer at Intel Corporation, where he leads the Partial Reconfiguration User flow team to develop end-to-end solutions for customers. Swapnil is proficient in Partial Reconfiguration Flow, including complete user experience from design flow, compiler flow, floorplanning, verification of software flow, simulation, and hardware debugging experience. He has also developed example designs and created user guides for better customer adoption of technology. Swapnil has worked with customers on issues and architecture and helped in planning the roadmap. With over 5 years of relevant experience, Swapnil has a deep understanding of VLSI – Design, Architecture, FPGA, Validation, Testing, Integration, and experience of memory as well as serial protocols such as AMBA protocols – AXI, AHB, and APB. He has also worked on Xilinx Vivado and ISE, Spartan 3E, Spartan 6, Artix 7, Kintex 7, and Xilinx Zynq 7000 series SoC. Swapnil has implemented basic protocols such as I2C and SPI protocol (On FPGA) and is familiar with Shell Scripting and Perl. Swapnil's educational background includes a Bachelor of Technology in Electronics and Communications Engineering from Rajarambapu Institute of Technology, Rajaramnagar, Sakharale. He has also worked as an FPGA Design Engineer at SQ.M Technologies and as an intern at Bhabha Atomic Research Centre, where he worked on a research project in VLSI Domain, development of an FPGA Based Time to Digital Converter, using VHDL language and tools such as Xilinx ISE Design Suite 14.7, FPGA Editor, Chipscope, and Modelsim. Swapnil is a dedicated professional with a passion for innovation and a deep understanding of FPGA/RTL design engineering. He is always willing to learn and is committed to delivering high-quality solutions to customers.