About

Vaibhavi Rastogi is a Senior Engineer at Samsung Semiconductor India R&D (SSIR), where she works as a SOC Design Verification Engineer in the Flash Controller team of the Memory Solutions group. With a Bachelor's degree in Electrical and Electronics Engineering from Birla Institute of Technology and Science, Pilani, Vaibhavi has 3.20 years of relevant experience in the field. At Samsung, Vaibhavi started as a Student Trainee and worked in the Memory Solutions group as part of the SOC verification team. She was responsible for verifying client and enterprise Solid State Drive (SSD) based SOCs and learned System Verilog and UVM. She also designed a generic sideband GPIO Agent and worked on the RTL verification of SAS based memory controllers involving AXI and AHB interfaces. Vaibhavi was involved in coding test cases according to the test plan/specification and debugging using Cadence Verdi and Synopsys Simvision tool. Additionally, she worked on Hardware-Software Co-simulation-C based firmware coding and debug using Synopsys Indago tool and firmware environment files. Vaibhavi ported and verified about 70+ test cases from SV to Unit FW by configuring SFRs in a .C file or through the backdoor deposit method, and reported firmware functionality requirements on a feature-basis. She was also involved in running the test regressions and debugging failing tests to isolate the root cause of failure. Vaibhavi's education history includes a Bachelor of Engineering (B.E.) degree from Birla Institute of Technology and Science, Pilani, where she studied Electrical and Electronics Engineering. She also attended Allahabad Public School and Delhi Public School, Allahabad, for her high school education. Vaibhavi's tech stack includes Mobile and Test.