About

Vandna Dhingra is a highly skilled Senior Engineer at Qualcomm with over 6 years of experience in Physical Design Engineering. She specializes in back-end engineering for the Physical Design department and has worked on high-frequency chip closure at lower technology nodes such as 45nm and 16nm. Vandna has hands-on experience in the flow RTL to GDS-II using EDA tools. Her key experiences include synthesis, floor-planning, placement and routing, and EDA capability. She has worked on Design-Compiler with IP hardening by RTL hacking, reducing power and area at synthesis using SPG and WLM modelling. Vandna has a good grasp of board-level requirement and thus understanding logical connectivity so as to prepare a refine placement strategies. She has also worked on timing vs congestion trade-off for SoC with huge logic size and attained successful closure. Her knowledge of building standalone H-TREE is commendable. Vandna's EDA capability includes Design-Compiler (Synopsys), STAR RC, Innovus (Cadence), and ICC2 (Design Planning). Vandna has a strong understanding of Physical Design Flow and its correct applications. She is knowledgeable in TCL based scripting and flow development. Her strong interpersonal, communication, and management skills make her an asset to any team. She has excellent debugging and problem-solving skills and is always interested in learning more and becoming more efficient. In addition to her current role at Qualcomm, Vandna has previously worked as an Engineer at Qualcomm in the Physical Design department. She has also provided an Alumni lecture to 3rd Semester folks on basics of Engineering and how they can proceed with their studies and eventually with their career at Nirma Institute of Technology, where she completed her Bachelor of Technology (B.Tech.) in Electrical, Electronics and Communications Engineering. Vandna also holds an SSC degree in Science from Maheshwari Vidyapeeth. Overall, Vandna Dhingra is a highly skilled and experienced Senior Engineer with a strong background in Physical Design Engineering and a passion for continuous learning and improvement.