About

Varun Palivela is a highly skilled Senior Staff Engineer with a passion for computer architecture and digital logic design. With over 10 years of relevant experience, Varun has a proven track record of success in CPU micro-architecture definition, analysis, performance modeling, and RTL Design. Currently working at arm as a Staff Engineer, Varun is responsible for the CPU micro-architecture definition, analysis, and performance modeling of the next-generation Arm Cortex-M processor, specifically the Load-Store Unit/Memory Subsystem and Branch Predictor. Prior to his current role, Varun served as a Senior Staff Engineer at Qualcomm, where he was responsible for CPU micro-architecture and RTL Design, specifically the Load-Store Unit (LSU). He also worked at Nuvia as a Member of Technical Staff, where he played a key role in the micro-architecture definition and RTL design for the Load-Store Unit. Varun holds a Master of Science in Computer Engineering from the University of Southern California and a Bachelor of Engineering in Electronics and Communication from Andhra University. He is highly skilled in software engineering, and his technical stack includes a wide range of tools and technologies. Varun is a highly motivated individual who loves challenges and is always looking for new ways to expand his knowledge and skills. He is an excellent communicator and collaborator, with a proven ability to work effectively as part of a team. With his extensive experience and expertise in CPU micro-architecture and RTL Design, Varun is a valuable asset to any organization.