About

Venkat TS is an experienced ASIC Design Engineer with expertise in Verilog, VHDL, RTL, FPGA, DSP, and MATLAB. With over 11 years of experience in the field, he has worked in both Hyderabad and Bangalore, and is currently seeking full-time employment in the area. In addition to his ASIC design skills, Venkat is also experienced in Verification Engineering, with a focus on UVM and System Verilog. He has worked in Hyderabad, Bangalore, and Pune, and has 3 to 10 years of experience in this area. Venkat also has experience in PNR Physical Design, with skills in Floor Planning, STA, PNR, and ICC2. He has 3 to 15 years of experience in this area and is based in Hyderabad. Furthermore, Venkat has expertise in DFT Engineering, with experience in tools like Mentor or Synopsys, FastScan, Boundary Scan, ATPG, JTAG, BIST, and Test compress. He has over 3 years of experience in this area and is based in Hyderabad. Finally, Venkat has experience as a PHY System Engineer, with skills in 802.11 a/b/g/n PHY standards, OFDM, algorithms, MAC, MatLab, and C. He has over 5 years of experience in this area and is based in Bangalore and Hyderabad. Venkat's current role is Recruitment Coordinator at a confidential company, where he specializes in Semiconductors and IT Technologies, including ASIC RTL Design and Verification, DFT, Physical Design, STA Synthesis, VOIP/VOLTE Engineers, Embedded C, C++, WLAN/GPU Linux Device Drivers, LLVM Compilers, Wireless 802.11, Bluetooth, 5GNR, NB-IOT, Stack-Layer2/Layer3, RF, and Multimedia Technologies. He also has expertise in IOT, Mobile (IOS/Android) Apps Technologies, Front End and Back End Developers, and AI Developers. In terms of technical skills, Venkat is proficient in AI, iOS, Mobile, Frontend, Backend, test, Android, and C. Overall, Venkat has 10.86 years of relevant experience and is seeking full-time employment in Hyderabad.