Say no to manually filling long application forms
Visit any careers page and a lightning button will pop up on any compatible page with a form
Use ChatGPT to auto-fill job forms
Ask for Referral for any job post
Vijeta Mahale
Senior Engineer at HARMAN International
About
Vijeta Mahale is a Senior Software Engineer at HARMAN International with around 5 years of experience in Embedded C development in automotive. She has a versatile knowledge of various communication protocols like CAN, Ethernet, FR, TCP/IP, LIN and has hands-on experience in working on Multicore ECU with Autosar architecture on hardware platforms such as MPC5748G and TI tda3xx and dra78xx. She is well-versed in UDS(ISO 14229) and DOIP (ISO 13400), and has configured, integrated, and tested AUTOSAR BSW modules (EthTsyn and CanTsyn) and MCAL(ethernet driver and EthTrcv for TI). She has worked on MCAL bringup for TI. Vijeta has developed cpp socket programming as a client application for diagnostic feature using dll and has hands-on experience with various tools for integration and application testing such as Canoe, Canalyzer, wireshark, logcat, dmesg, and debugging tools such as Trace 32 lautcherbach and Code composer studio. For audit topic, unit testing using gtest and LDRA, design diagrams using Enterprise architect. She has worked with IPC mechanism specifically AF_UNIX and shared memory. She has experience in working with pthread and signaling in Linux. Vijeta has worked as a senior software engineer in project "Gateway module" in KPIT where she tested various modules such as Diagnostics, application layer testing, Gateway functionality, time synchronization, Ethernet switch, Doip, CDD, Network management. She has debugged and fixed several issues in DCM, application layer, Tsynch, configuration of CAN and FR layers, lintp, and has knowledge of modules such as CANIF, PDUR, FRIF, COM, RTE, OS, ETHIF, ETHTsync, CANTSynch, STBM, Ethtrcv, lintp, cantp. She has interacted with customers for understanding and development of test cases for Tsynch. She has developed CAPL and Python tool for gateway functionality and time synchronization functionality and software download, and implemented the requirement for the CDD module. Vijeta holds a Bachelor of Engineering (B.E.) in Electrical and Electronics Engineering from KLESCET, Belgaum. She also completed her Science education from M E S Chaitanya P U College, Sirsi, and 10th std from M E S English Medium
Education Overview
• klescetbelgaum
• m e s chaitanya p u college sirsi
• m e s english medium high school sirsi
Companies Overview
• harman
• kpit
Experience Overview
7.8 Years
Find anyone’s contact
Experience
Skills
Boost your visibility and stand out to employers with referrals from your LinkedIn connections.
architecture
C++
Communication
Embedded Software
Ethernet
Integration
Internet Protocol Suite (TCP/IP)
linux
Python
Software Engineer
switches
TCP/IP
test
test cases
testing
Wireshark
Contact Details
Email (Verified)
xxxxxxxx@xxxx.xxMobile Number
+91XXXXXXXXXXEducation
klescetbelgaum
Bachelor of Engineering (B.E.)
2012 - 2016
m e s chaitanya p u college sirsi
Science
2010 - 2012
m e s english medium high school sirsi
10th std
2005 - 2010
Frequently asked questions
Find anyone’s contact and let Weekday reach out to them on your behalf
Start hiring nowStop manually filling job applications. Use AI to auto-apply to jobs
Look for jobs now