vikram murali
physical design engineer
About
Vikram Murali is a highly experienced physical design engineer with over 12 years of relevant experience in the industry. Currently working at Intel, he has previously worked at Samsung Austin R&D Center and Texas Instruments in various engineering roles. Vikram holds a Bachelor's degree in Electronics and Communications Engineering from Anna University and a Master's degree in Electrical Engineering from the University of California, San Diego. He has also completed several courses in VLSI design and physical design. Throughout his career, Vikram has demonstrated expertise in physical design, floor planning, power grid design, clock tree synthesis, and timing closure. He has been involved in designing complex chips for various applications, including mobile, server, and networking. His experience in IC design for manufacturability has been instrumental in ensuring that the designs are optimized for manufacturing and yield. Vikram's technical skills are complemented by his excellent communication and teamwork abilities. He has worked with cross-functional teams and collaborated with designers, architects, and verification engineers to deliver high-quality designs. His experience in mentoring and training junior engineers has also contributed to the growth of his team. In summary, Vikram Murali is a highly skilled physical design engineer with a strong academic background and over a decade of relevant industry experience. He has a proven track record of delivering complex designs and working collaboratively with cross-functional teams.
Education
• uc san diego
• anna university
• rajalakshmi engineering college anna university
Companies
• intel
• samsung austin rd center
• texas instruments
• uc san diego health
• leitner ag brand leitwind
Experience
13.3 Years
Experience
Skills
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analog circuit design
asic
c
c++
cadence
cadence spectre
cadence virtuoso
cadence virtuoso layout editor
cadence virtuoso xl
circuit design
computer architecture
creative writing
Design
design for manufacturing
design for test
digital circuit design
drc
elocution
encounter
equivalence checking
functional verification
integrated circuit design
logic design
logic synthesis
lvs
perl
physical design
physical verification
public speaking
rtl design
rtl verification
simulations
soc
solid state physics
spice
static timing analysis
synopsys primetime
synopsys tools
tcl
technical presentations
verilog
vlsi
Contact Details
Email (Verified)
murXXXXXXXXXXXXXXXXXXomMobile Number
+16XXXXXXX37Education
uc san diego
2009 - 2011
anna university
2005 - 2009
rajalakshmi engineering college anna university
2005 - 2009
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