About

Vineet Sachan is a Senior R&D Manager at Synopsys with over 20 years of experience in memory circuit design. He has worked on various technologies ranging from 21um to 10nm, 7nm, and 5nm. Vineet specializes in automotive memory compilers and has achieved first pass silicon success on many memories, including SRAM and ROM. He has also been involved in automotive platform development, including Aging, Safety manual, FMEDA, and DFMEA development. Vineet's current role at Synopsys involves the development of all types of automotive memory compilers. Prior to this, he worked as an R&D Manager at Synopsys, where he developed the latest technology SRAM memory compilers. He also worked at AMD as a Manager Design Engineering, where he delivered GF20LPM memory compilers successfully with working silicon, including HD1P, RF2P, and PDP with multiple types of bitcells. Vineet holds a BE degree in E&C from the Indian Institute of Technology, Roorkee, which he completed in 2000. He also attended Saraswati Shishu Mandir, Charkhari, from 1980 to 1985. With 22.96 years of relevant experience, Vineet is a seasoned professional in memory circuit design. He has a proven track record of delivering successful projects and achieving first pass silicon success. Vineet's expertise in automotive memory compilers and platform development makes him a valuable asset to any organization.