About

Vivek Pandit is a highly skilled Software Engineer II at Cadence Design Systems with over 6 years of relevant experience in the field. He is a dedicated and hardworking individual who is always eager to learn and take on new challenges. Vivek’s expertise lies in RTL Integration to SoC, Reachability tests development for SoC, C Based Test Development and debug, Automation infrastructure development, Debugging/Problem Solving Skill, EDA Tools (JasperGold- SuperLINT, FPV, Coverage App), EDA Tools - VManager, IMC, SV/UVM, C++, PERL Based Design/Development, Verilog HDL Coding, AMBA Bus (APB/AHB/AXI) Protocol, Verification Tool Development, Top Level ARM based CPU Verification, ARM Architecture, Multi-Processor (MP) Random Instruction Sequence (RIS) Tool, and HSPICE. In his previous role as a Graduate Engineer at ARM, Vivek worked on Top Level Verification of ARMv8 based Core/CPU, where he was responsible for test scenario development, modifying/adding an existing template, generating random test cases with it, running it on core/RTL, analyzing and debugging failures. He also worked closely with RTL designer/team for filed RTL bug until it resolves, developed top-level templates for RIS tool to recreate corner case RTL bug, and wrote System Verilog based coverage for system registers and assertion. Additionally, Vivek mentored new team members on ARM based core overview, validation flow, using debugging tool effectively, categorizing, and debugging failures. Vivek holds a Master of Technology (M.Tech.) degree in VLSI Design from Nirma University, Ahmedabad, Gujarat, India, and a Bachelor's Of Engineering degree in Electronics & Communication Engineering from a. d. patel institute of technology. With his extensive knowledge and experience in software engineering, test, integration, infra, qa, and design, Vivek is an asset to any team he works with. He is always excited to explore new opportunities in the Design(RTL)/Verification domain and is ready to take on new challenges.