About

Wasiq Zia is a highly experienced Design Verification Engineer currently working at Hailo. He specializes in VLSI designs with a focus on standard protocols and models. With 15.36 years of relevant experience, Wasiq has honed his skills in front-end verification tools and IP packaging. Wasiq's primary interest lies in SoC verification using System Verilog, UVM, C, C++, and SystemC. He is proficient in a range of programming languages, including Specman, System Verilog, VHDL, C, and C++. He is also well-versed in a variety of protocols such as Wireless LAN, Time Sensitive Networks (TSN), Ethernet, USB 3.x, USB4, I2C, JTAG, and DisplayPort. Prior to his current role at Hailo, Wasiq worked as a Software Architect at Cadence Design Systems. He has a Bachelor's degree in Electronics and Communication from Jamia Millia Islamia, which he obtained in 2007. He also holds an AISSE degree in Science from Fr. Agnel, which he earned in 2003. As a frontend and senior software engineer, Wasiq has a keen eye for detail and a passion for delivering high-quality work. He is a skilled Verification IP Developer who is always looking for new challenges and opportunities to learn and grow. With his extensive experience and expertise, Wasiq is a valuable asset to any organization he works with.