About

Yashika Gupta is a Product Validation Engineer 1 at Cadence Design Systems with a strong background in power optimization R&D. She specializes in creating and verifying power reduction techniques and flows at RTL scale, and has extensive experience in unit testing and regression analysis. With an in-depth knowledge of bash scripts and Tcl, Yashika is also skilled in benchmark design analysis and customer design debugging. Yashika completed her B.TECH in Electronics & Communication Engineering in 2021 and has a strong foundation in digital electronics. She is proficient in HDL (Verilog), HVL (System Verilog), and scripting languages such as PERL, C-shell, and TCL. She also has experience with communication protocols such as UART, I2C, and SPI, as well as programming languages like C and data structures. Yashika is familiar with tools such as Questa-Sim, Xillinx-ISE, Proteus, and EDA Playground, and is comfortable working on both Windows and Linux platforms. Yashika has a good understanding of RTL Synthesis concepts and Testbenches in Verilog and System Verilog, and is proficient in writing System Verilog Testbench Environment. She has 1.43 years of relevant experience and previously worked as an intern at 3st Technologies. Yashika's education history includes a Bachelor's degree in Electronics and Communications Engineering from YMCA, which she completed in 2021. Overall, Yashika is a skilled Product Validation Engineer with a strong background in power optimization R&D, programming, and scripting. She is a quick learner, detail-oriented, and has excellent problem-solving skills.